Exemplary embodiments relate to a non-volatile memory device and a method of manufacturing the same and, more particularly, to a three dimensional (3-D) structured non-volatile memory device and a method of manufacturing the same.
A non-volatile memory device is a memory device that retains data although the supply of power is stopped. As an increase in the integration degree of 2-D structured memory devices fabricated in a single layer on a silicon substrate recently is reaching physical limits, a 3-D structured non-volatile memory device in which memory cells are vertically stacked from the silicon substrate is being developed.
The structure and features of the 3-D structured non-volatile memory device are described below with reference to FIG. 1.
FIG. 1 is a cross-sectional view of a known 3-D structured non-volatile memory device.
As shown in FIG. 1, the known vertical channel type non-volatile memory device includes a lower select transistor LST, a plurality of memory cells MC, and an upper select transistor UST which are stacked along channels CH protruded from a substrate 10 including a source region S. Here, the plurality of memory cells MC is coupled in series between the lower select transistor LST and the upper select transistor UST to form one string STRING, and each string is coupled to a bit line BL. In this structure, the integration degree of the memory devices may increase because the strings are vertically arranged from the substrate 10 as compared with a known flat plate type (2-D) memory device.
The lower select transistor LST includes a channel CH, a gate insulating layer 13 surrounding the channel CH, and a lower select line 12. The upper select transistor UST includes a channel CH, gate insulating layers 13 and 19 surrounding the channel CH, and an upper select line 18. Reference numerals ‘11 and 17’ denote interlayer dielectric layers.
The plurality of memory cells MC include a channel CH, a tunnel insulating layer surrounding the channel CH, a charge trap layer, a charge block layer 16, and word lines 15. Reference numeral ‘14’ denotes an interlayer dielectric layer.
In this structure, after the word lines 15 are formed, the charge block layer, the charge trap layer, and the tunnel insulating layer 16 are sequentially formed and the channels CH are formed. Here, the manufacturing process is different from the process of manufacturing the flat plate type non-volatile memory device. Accordingly, the film quality of the tunnel insulating layer already formed may deteriorate in the process of forming the channels CH, and thus characteristics of the memory device may deteriorate.